Home » Product List » DDR3 Ram memory » 1GB 2GB 4GB 8GB DDR3 RAM
Product Details
1GB 2GB 4GB 8GB DDR3 RAM
| Packing: | Carton Packing ,Bulk Packing ,OEM Original Packing |
|---|---|
| Standard: | 0.8kg |
| Productivity: | 100000PCS/Year |
| Unit Price: | Negotiable |
| Shipment Terms: | FOB |
| Payment Terms: | T/T,Western Union |
| Minimum Order: | 5 Pieces |
| Price Valid Time: | From Nov 26,2011 To Nov 26,2012 |
| HS Code: | 84717090 |
| Trademark: | 123 |
| Origin: | China |
| Frequency: | 1333MHz |
| Application: | Laptop |
| Memory Type: | DDR3 |
| Memory Capacity: | 4G |
| Compatibility: | Full Compatibile With All Motherboards, Intel, Amd |
| Export Markets: | North America, South America, Eastern Europe, Southeast Asia, Africa, Oceania, Mid East, Eastern Asia, Western Europe |
1GB 2GB 4GB 8GB DDR3 RAM
128MB/256MB/512MB/1G/2G.
Desktop Computer, laptop computer.
128MB/256MB/512MB/1G/2G.
1) DDR 400/333 & DDRII 533/667/800 & DDR3 1333 MHz.
2) 168/184/240-pin socket type dual in line memory module (DIMM).
3) 2.6V power supply
4) Data rate: 400/333/533/667/800Mbps (max).
5) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8Vpower supply for DDR II products
6) Double-data-rate architecture, two data transfers per clock cycle.
7) Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be
Used in capturing data at the receiver
8) Data inputs and outputs are synchronzed with DQS.
9) DQS is edge aligned with data for read, center aligned with data for write.
10) Differential clock inputs (CK and CK).
11) DLL aligns DQ and DQS transitions with CK transitions
12) Commands entered on each positive CK edge: Data and data mask referenced to
Both edges of DQS.
13) Four internal banks for concurrent operation (component).
14) Data mask(DM) for write data.
15) Auto precharge option for each burst access
16) Programmable burst length: 2, 4, 8
17) Programmable/CAS latency (CL): 3
18) Programmable output driver strength: Normal/weak
19) Refresh cycles: (8192 refresh cycles/64ms).
20) 7.8US maximum average periodic refresh interval.
21) Posted CAS by programmable additive latency for better command and data bus
Efficiency
22) Off-chip-driver impedance adjustment and on-die-termination for better signal quality.
23) DQS can be disabled for single-ended data strobe operation
24) 2 variations of refresh
25) Auto refresh
26) Self refresh.
Inquiry Basket (












